1. Technical Field
The embodiments described herein relate to a semiconductor integrated apparatus, and more particularly, to a buffer circuit of a semiconductor integrated apparatus.
2. Related Art
In general, a buffer circuit of a semiconductor integrated apparatus is provided to supply a stabilized voltage to an internal circuit. Here, the buffer circuit is configured to receive a reference voltage and generate an internal voltage having the same level as the reference voltage.
FIG. 1 is a schematic circuit diagram of a conventional buffer circuit of a semiconductor integrated apparatus. In FIG. 1, a buffer circuit 10 has a current mirror structure receiving an input voltage V_in from an exterior of the buffer circuit 10 and generating a stable output voltage V_out. The buffer circuit 10 includes first to tenth transistors P1 to P5 and N1 through N5. The first and second transistors P1 and P2 receive a first bias voltage BIAS1 through gate terminals and a supply voltage ‘VDD’ through source terminals, and output a constant voltage through drain terminals. The third and fourth transistors N1 and N2 have gate terminals connected to a common node, and are connected to the drains of the first and second transistors P1 and P2, and receive the constant voltage. Here, the gate and drain terminals of the third transistor N1 are connected with each other, and therefore, the gate and drain terminals of the third transistor N1 and the gate terminal of the fourth transistor N2 receive the same potential level.
The fifth and sixth transistors P3 and P4 have source terminals to which the source terminals of the third and fourth transistors N1 and N2 are connected, and gate terminals connected to a common node. Here, the gate and drain terminals of the fifth transistor P3 are connected with each other. The seventh and eighth transistors N3 and N4 receive a second bias voltage BIAS2 through gate terminals, and have drain terminals connected to the drain terminals of the fifth and sixth transistors P3 and P4 and source terminal connected to a ground voltage ‘VSS’.
The input voltage V_in is supplied to a node to which the third transistor N1 and the fifth transistor P3 are connected, and an output node A, from which the output voltage V_out is output, is connected to a node to which the fourth transistor N2 and the sixth transistor P4 are connected. In addition, a pull-up signal ‘pu’ is output from a node to which the second transistor P2 and the fourth transistor N2 are connected, and a pull-down signal ‘pd’ is output from a node to which the sixth transistor P4 and the eighth transistor N4 are connected.
The ninth transistor P5 has a gate terminal through which the pull-up signal ‘pu’ is input and a source terminal to which the supply voltage ‘VDD’ is supplied. The tenth transistor N5 has a gate terminal through which the pull-down signal ‘pd’ is input, a drain terminal to which the drain terminal of the ninth transistor P5 is connected, and a source terminal which is connected to the ground voltage ‘VSS’. At this time, the output node A is connected to a node to which the ninth transistor P5 and the tenth transistor N5 are connected.
In the buffer circuit 10, if the level of the input voltage V_in increases, then the potential level of the pull-up signal ‘pu’ decreases, and the turn-ON of the ninth transistor P5 quickly occurs. Accordingly, the level of the output voltage V_out increases. Conversely, if the level of the input voltage V_in decreases, then the potential level of the pull-down signal ‘pd’ increases, and the turn-ON of the tenth transistor N5 quickly occurs. Accordingly, the level of the output voltage V_out decreases.
However, buffer circuit 10 suffers from defects in that, since it is composed of the transistors, as described above, it is influenced by process variations.
A normal buffer circuit must generate the output voltage V_out having the same level as the input voltage V_in. Accordingly, by measuring the level of the output voltage V_out in response to the input voltage V_in, as can be readily seen from FIG. 2, the level of the input voltage V_in and the level of the output voltage V_out do not correspond to each other. This non-correspondence in the levels of the input and output voltages V_in and V_out results from changes in the sizes of the ninth and tenth transistors P5 and N5 that function to actually perform pull-up and pull-down operations in the buffer circuit 10. Here, the sizes of transistors are determined by photolithographic processes. Accordingly, as semiconductor integrated apparatuses trend toward fine formation, errors are likely to occur while conducting the photolithographic processes. Thus, the sizes of transistors may deviate from a predetermined range.
For example, if the tenth transistor N5 is formed large relative to the other transistors due to the process variations, as can be readily seen from the graph of FIG. 2, the level of the output voltage V_out decreases compared to the level of the input voltage V_in. On the contrary, if the ninth transistor P5 is formed large relative to the other transistors, then the level of the output voltage V_out increases compared to the level of the input voltage V_in.
Thus, in the buffer circuit 10, it is difficult to generate precisely an internal voltage.